Study of the physico-structural properties of semiconductor thin-film devices

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This study aims to optimize hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) by examining the effects of gate dielectric and active layer parameters through SILVACO ATLAS simulations. A validated reference structure, matching experimental I-V data with 99% accuracy, was used to investigate three critical factors: gate dielectricthickness, dielectric material properties (high-κ vs. low-κ), and active layer thickness.Varying the Si3N4 dielectric thickness from 300 nm to 15 nm showed that thinner layers improved device performance, with VT = 4.86 V, μFE ≈ 0.1 cm2/V·s, SS = 0.47 V/decade,and Ci = 2.21×10−8 F/cm2. Parameters followed exponential and linear trends with thickness, modeled as P = P0 + α·exp(β·di), except SS. A range of dielectric materials (κ = 3.9–300) was tested; SrTiO3 emerged as the best, yielding IDS = 2.82×10−5 A, Ci = 2.65×10−9 F/cm2, VT = 3.9 V, μFE = 0.0603 cm2/V·s, Ion/Ioff = 6.28×107, and SS = 0.7691 V/decade. Scaling the active layer thickness from 300 nm to 15 nm significantly enhanced performance: higher Ion (5.91×10−6 to 2.97×10−4 A), lower Ioff (1.29×10−11 to 2×10−18 A), higher Ion/Ioff, and μFE rising exponentially (0.10 to 14.55 cm2/V·s), with linear drops in VT and SS. An optimized TFT structure using SrTiO3 and 15 nm thick layers achieved VT = 3.21 V, Ci = 1.77×10−5 F/cm2,Ion = 0.609 A, Ioff = 8.28×10−20 A, Ion/Ioff = 7.36×1018, and peak field = 9.5×105 V/cm. These results underline the promise of high-κ dielectrics and geometric scaling for advanced flexible, transparent, and energy-efficient electronics.

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