Number theoretic transforms (NTTs) , unlike the Di.screte Fourier Transform (DFT), are defined in finite rings or fields of integers rather than in the field of complex numbers. A major advantage of NTTs is that they ar'p n(lt s'lbject to round off or truncation errors and can be used ta compute error free, fast and efficjent, digital convalutions and l;orre la t ions . In partJicular, the NTTs with a modlJlus of the form Ft=2b+l where b=2t and referred to as the Fermt:!.t number transforms (FNTs) , seem particularly attractive. These t,ransforms have t,he advantage that their transform lengths are a power of two, thllS making the Fast Fouri~r Transform algorithms (FFT) applicable for their cornputationFull custom VJJSI technology can be us~d ta lmplement FNTs since the constrain ts assoc ia ted wj. th the pecu l j.ar arithmetic of (b+1.) bits present no difficulty of implementation as for the standard 8-, 16 or 32-bit mjcroproce~sors. In this thesis two cascadable FNT section circuits were implemented using a 2.511m CMOS process.The first (~irc,lit lIses a=2 as the basic funcTion or the Nth root of the unjty, where N is transform length, and exploits ail the advanta,g~s of the techniques already rleveloped. The chip real j.sed ha,s clear advanta,ges in terms of speed, power consllmpt i on and area . In the second design a been chosen as {2 to dollble the tran~form l~ngth. ince powers of 2 are also powers of !2 the impl~ment:atjorl has been simplified. The design ha~ resulted in a rhi.p tha,t can be ca,scaded along wjth the resi due multipl ier designed to constrtlct 1:1 f~st (:onvolver , Comparisons with the commer<'ially available DSP chjps have been made and conclusion drawn on the feasibility of employing the FNT for convoluti.ons .