Digital decimator for spectrum analyser

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The main objectives of this project, which were to design, construct and program a system decimator for Fourier analyser were achieved. The software developed to implement the structure of the multistage decimators was successful since it met the required objectives. Therefore different decimation filters were implemented and tested by the simulator program. The purpose of the hardware design is to build a low cost system decimator based on the TMS320l0.The substitution of the complex and expensive analogue low pass filters by the TMS320l0 was successful since the cost of the digital system is rouch less than the analogue system. The commercially available instruments paya high penalty for a Fourier analyser with a high performance analogue antialiasing low-pass filters. The " cost of the present systero decimator can be reasonable considering the high speed and accuracy provided. The cost of the constructed hardware part was approximately However, this is not to say that the system as it stands is perfect in all aspects. The technique of the multistage decimation revealed that it can be adopted in the processing of signal for Fourier analyser. Also the digital implementation cost may well be 5 to 10 times smaller using the TMS32010.